Abstract
PCB traces in backplane are typically routed as striplines, which create near end crosstalk, but no far end crosstalk theoretically. However, in practice both near end and far end crosstalk introduced by via antipads and layer misalignment in the connector pin field in large volume production can be very significant. This paper presents an analysis for the first time to quantify PCB trace crosstalk in the connector pin field of high speed backplanes. Crosstalk from the adjacent differential pairs on the same layer and in particular from neighboring layers is first modeled and simulated. Both the PCB design tolerance and the routing constraints in the connector pin field are discussed. The model is then correlated with a 10ps edge TDR measurement. Finally, the simulated and measured results are provided to demonstrate the significance of the crosstalk due to connector pin field traces.
I. Introduction
The crosstalk takes a more significant role in today's high speed design as the speed of the interconnect increases to multi-giga bit data rates. Figure 1 shows the measured insertion loss and crosstalk of a typical backplane. At 2.5GHz, the crosstalk is as large as the signals which make it very difficult for this particular backplane to operate at 5Gbps. Since the crosstalk can be large relative to signals, it is important to accurately model the crosstalk in practical designs.
The largest source of crosstalk for a typical backplane channel usually comes from the connector via structure, even if the ground via are inserted between the differential signal via pairs. The amount of crosstalk is largest for the bottom layer traces since the longer via length creates more coupling. However, the crosstalk due to PCB traces is not negligible either, even though the PCB traces are typically routed as striplines in backplanes. A typical backplane routing consists of many traces through connector slots in multiple layers. The increasing routing density forces the traces closer to via pins as the traces pass through the connector via region. For most of the high speed backplane design, the traces are routed differentially to maintain 100 ohm differential impedance. As the differential traces are routed through a dense connector via area, the pair of traces must go through via pin filed with very tight design rules. In some cases, the two differential traces can be routed together between two vias while maintain the differential mode. However, many differential traces have to be routed in single-ended in connector pin field because via space is too narrow to allow two traces passing between two vias as shown in Figure 2. The limited choices of PCB stackup and the trace widths constrains the placement of the trace in order to maintain specified impedance and avoiding crosstalk from adjacent traces.
To insure the traces have adequate ground reference, the stripline traces need to have solid ground planes on top side and bottom side. The ground planes not only provide 100 ohm differential impedance, but also isolate the coupling between the traces routed on the top and bottom of the ground layer. However, in the connector pin field the connector pins create many anti-pad holes on the ground plane. To meet the impedance requirement, the anti-pad diameter is usually enlarged. The enlarged anti-pad on the ground plane may cut off the ground plane under the trace area. Since the design space is so tight in the connector pin field, the differential traces are usually placed right on the edge or even within a few mils of the anti-pad boundary. Consequently, this will not only increase the impedance of the differential traces, but fail to isolate the signal crosstalk between the differential traces on top and bottom of the ground plane. Figure 3 shows an example of routing where traces on layer N and N+1 are exposed by 2~3mil without the ground planes.
Usually, the tolerance of layer-to-layer registration is much worse for the layers not within the same core. It is not unusual for a 6 mil trace shifted side ways by the same amount relative to the other core in volume production. If the traces are placed at the edge of the anti-pad boundary which belongs to a different core, the anti-pad hole may completely cut off the trace ground reference in the worst case tolerance. Therefore, the trace crosstalk occurs between traces in the same layer as well as in the adjacent layers. The amount of crosstalk is a strong function of manufacturing tolerances. This type of crosstalk is inherently 3D in nature and has not been studied in detail in the past.
In this paper, we present measurement and modeling of PCB trace crosstalk in backplane connector pin fields. We first obtain scattering parameters of three differential pairs using full-wave 3D field solvers. We then simulate the time domain response and correlate it with an 10ps edge TDR measurements.
II. Simulation and Measurement Correlation
To understand the worst case talk effect, the crosstalk is simulated with full wave 3D tools. The manufacturing tolerance of layer-to-layer registrations which affect the anti-pad and trace alignment is considered in the design. The trace width and dielectric thickness are also part of the simulation parameters. The simulation includes nominal case and worst case tolerance design. The simulated backplane is based on a typical connector backplane. The backplane connector has ~2 mm via-to-via separation.
Both horizontal crosstalk and vertical crosstalk are considered in the simulation as illustrated in Figure 4. Figure 5 shows the 3D model. The horizontal crosstalk occurs between two neighboring differential traces routed on the same layer. The vertical crosstalk happens between adjacent layers separated by ground layer. Since the ground layer is full of antipad holes, the ground layer isolation is not as good as expected. The offset of the antipad exposed the traces, routed above and below the ground plane, to each other. This may create large crosstalk depending on the manufacture tolerances. Figures 6 and 7 show the simulated vertical (different layer) and horizontal (same layer) differential near end crosstalk. Since the crosstalk percentage is observed at the connector pin field, the crosstalk magnitude will be reduced at the receiver package after the crosstalk noise travel through the PCB traces on the daughter card. Since the aggressor channel can be activated at any time, the maximum near end crosstalk from all three neighboring pairs can be added up to 1.5% as shown in Figure 8. Since the near end crosstalk quickly reaches its maximum magnitude, the crosstalk does not get worse for signals travel through multiple connector pin field. However, the far end crosstalk accumulates the energy if the crosstalk occurs over multiple connector pin field. Fortunately, the far end crosstalk magnitudes attenuate significantly with slower edge rate as it travels to the far end of the receiver. The Table 1 shows the far end crosstalk results at different edge rate from vertical coupling between adjacent layers.
Since the 1.5% trace near end crosstalk at the connector pin will be attenuated by the daughter card PCB trace and connector pins, the actual effect of the crosstalk at the receiver pin will be reduced. The amount of crosstalk attenuated from the connector to the receiver package was simulated. Since the simulation model includes the PCB trace, connector via and connector itself, it is very easy to reconstruct a model excluding the PCB trace and SMA model from the model. The results show the actual crosstalk reduced to 1.25% as shown in Figure 10 at the receiver package pin. For 1V differential swing, this means the crosstalk voltage at receiver is 12.5mV. For high speed links that have very little voltage margin, this effect could amount to significant system voltage margin loss.
To validate the simulation model, a typical backplane with missing ground plane by 2~3 mil anti-pad cut off as in Figure 3 was measured in time domain using a 10ps edge rate TDR launch, which provides a clear near end crosstalk measured at the SMA connector on the daughter card. Although the response waveform edge rate is reduced by the PCB and connector loss, the vertical trace crosstalk between two different layers can be observed from the TDR waveforms as in Figure 11. Figure 12 shows the near end and far end crosstalk correlation of a backplane channel measured at SMA connectors. Good correlation between measurement and simulation was achieved.
III. Conclusion
In summary, the near end and far end crosstalk due to PCB traces in connector pin field are not negligible for high speed backplanes. They could have important impact on system margin. Designers need to set the trace routing rule by including PCB design tolerance into the consideration. Make sure the differential trace edge is placed 5 mils away from the anti-pad boundary on the adjacent ground plane. Add this design rule on the backplane design check list. If the design space is not available, simulate the worst case based on the PCB design tolerance from the PCB vendor. The final product can be measured using 10ps TDR on corner board provided by the PCB vendor. The vendor may provide a cross section of PCB trace to verify the design tolerance.
PCB traces in backplane are typically routed as striplines, which create near end crosstalk, but no far end crosstalk theoretically. However, in practice both near end and far end crosstalk introduced by via antipads and layer misalignment in the connector pin field in large volume production can be very significant. This paper presents an analysis for the first time to quantify PCB trace crosstalk in the connector pin field of high speed backplanes. Crosstalk from the adjacent differential pairs on the same layer and in particular from neighboring layers is first modeled and simulated. Both the PCB design tolerance and the routing constraints in the connector pin field are discussed. The model is then correlated with a 10ps edge TDR measurement. Finally, the simulated and measured results are provided to demonstrate the significance of the crosstalk due to connector pin field traces.
I. Introduction
The crosstalk takes a more significant role in today's high speed design as the speed of the interconnect increases to multi-giga bit data rates. Figure 1 shows the measured insertion loss and crosstalk of a typical backplane. At 2.5GHz, the crosstalk is as large as the signals which make it very difficult for this particular backplane to operate at 5Gbps. Since the crosstalk can be large relative to signals, it is important to accurately model the crosstalk in practical designs.
The largest source of crosstalk for a typical backplane channel usually comes from the connector via structure, even if the ground via are inserted between the differential signal via pairs. The amount of crosstalk is largest for the bottom layer traces since the longer via length creates more coupling. However, the crosstalk due to PCB traces is not negligible either, even though the PCB traces are typically routed as striplines in backplanes. A typical backplane routing consists of many traces through connector slots in multiple layers. The increasing routing density forces the traces closer to via pins as the traces pass through the connector via region. For most of the high speed backplane design, the traces are routed differentially to maintain 100 ohm differential impedance. As the differential traces are routed through a dense connector via area, the pair of traces must go through via pin filed with very tight design rules. In some cases, the two differential traces can be routed together between two vias while maintain the differential mode. However, many differential traces have to be routed in single-ended in connector pin field because via space is too narrow to allow two traces passing between two vias as shown in Figure 2. The limited choices of PCB stackup and the trace widths constrains the placement of the trace in order to maintain specified impedance and avoiding crosstalk from adjacent traces.
To insure the traces have adequate ground reference, the stripline traces need to have solid ground planes on top side and bottom side. The ground planes not only provide 100 ohm differential impedance, but also isolate the coupling between the traces routed on the top and bottom of the ground layer. However, in the connector pin field the connector pins create many anti-pad holes on the ground plane. To meet the impedance requirement, the anti-pad diameter is usually enlarged. The enlarged anti-pad on the ground plane may cut off the ground plane under the trace area. Since the design space is so tight in the connector pin field, the differential traces are usually placed right on the edge or even within a few mils of the anti-pad boundary. Consequently, this will not only increase the impedance of the differential traces, but fail to isolate the signal crosstalk between the differential traces on top and bottom of the ground plane. Figure 3 shows an example of routing where traces on layer N and N+1 are exposed by 2~3mil without the ground planes.
Usually, the tolerance of layer-to-layer registration is much worse for the layers not within the same core. It is not unusual for a 6 mil trace shifted side ways by the same amount relative to the other core in volume production. If the traces are placed at the edge of the anti-pad boundary which belongs to a different core, the anti-pad hole may completely cut off the trace ground reference in the worst case tolerance. Therefore, the trace crosstalk occurs between traces in the same layer as well as in the adjacent layers. The amount of crosstalk is a strong function of manufacturing tolerances. This type of crosstalk is inherently 3D in nature and has not been studied in detail in the past.
In this paper, we present measurement and modeling of PCB trace crosstalk in backplane connector pin fields. We first obtain scattering parameters of three differential pairs using full-wave 3D field solvers. We then simulate the time domain response and correlate it with an 10ps edge TDR measurements.
II. Simulation and Measurement Correlation
To understand the worst case talk effect, the crosstalk is simulated with full wave 3D tools. The manufacturing tolerance of layer-to-layer registrations which affect the anti-pad and trace alignment is considered in the design. The trace width and dielectric thickness are also part of the simulation parameters. The simulation includes nominal case and worst case tolerance design. The simulated backplane is based on a typical connector backplane. The backplane connector has ~2 mm via-to-via separation.
Both horizontal crosstalk and vertical crosstalk are considered in the simulation as illustrated in Figure 4. Figure 5 shows the 3D model. The horizontal crosstalk occurs between two neighboring differential traces routed on the same layer. The vertical crosstalk happens between adjacent layers separated by ground layer. Since the ground layer is full of antipad holes, the ground layer isolation is not as good as expected. The offset of the antipad exposed the traces, routed above and below the ground plane, to each other. This may create large crosstalk depending on the manufacture tolerances. Figures 6 and 7 show the simulated vertical (different layer) and horizontal (same layer) differential near end crosstalk. Since the crosstalk percentage is observed at the connector pin field, the crosstalk magnitude will be reduced at the receiver package after the crosstalk noise travel through the PCB traces on the daughter card. Since the aggressor channel can be activated at any time, the maximum near end crosstalk from all three neighboring pairs can be added up to 1.5% as shown in Figure 8. Since the near end crosstalk quickly reaches its maximum magnitude, the crosstalk does not get worse for signals travel through multiple connector pin field. However, the far end crosstalk accumulates the energy if the crosstalk occurs over multiple connector pin field. Fortunately, the far end crosstalk magnitudes attenuate significantly with slower edge rate as it travels to the far end of the receiver. The Table 1 shows the far end crosstalk results at different edge rate from vertical coupling between adjacent layers.
Since the 1.5% trace near end crosstalk at the connector pin will be attenuated by the daughter card PCB trace and connector pins, the actual effect of the crosstalk at the receiver pin will be reduced. The amount of crosstalk attenuated from the connector to the receiver package was simulated. Since the simulation model includes the PCB trace, connector via and connector itself, it is very easy to reconstruct a model excluding the PCB trace and SMA model from the model. The results show the actual crosstalk reduced to 1.25% as shown in Figure 10 at the receiver package pin. For 1V differential swing, this means the crosstalk voltage at receiver is 12.5mV. For high speed links that have very little voltage margin, this effect could amount to significant system voltage margin loss.
To validate the simulation model, a typical backplane with missing ground plane by 2~3 mil anti-pad cut off as in Figure 3 was measured in time domain using a 10ps edge rate TDR launch, which provides a clear near end crosstalk measured at the SMA connector on the daughter card. Although the response waveform edge rate is reduced by the PCB and connector loss, the vertical trace crosstalk between two different layers can be observed from the TDR waveforms as in Figure 11. Figure 12 shows the near end and far end crosstalk correlation of a backplane channel measured at SMA connectors. Good correlation between measurement and simulation was achieved.
III. Conclusion
In summary, the near end and far end crosstalk due to PCB traces in connector pin field are not negligible for high speed backplanes. They could have important impact on system margin. Designers need to set the trace routing rule by including PCB design tolerance into the consideration. Make sure the differential trace edge is placed 5 mils away from the anti-pad boundary on the adjacent ground plane. Add this design rule on the backplane design check list. If the design space is not available, simulate the worst case based on the PCB design tolerance from the PCB vendor. The final product can be measured using 10ps TDR on corner board provided by the PCB vendor. The vendor may provide a cross section of PCB trace to verify the design tolerance.
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